SH7670 Datasheet, PDF (438/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 12 Ethernet Controller (EtherC)
12.3.10 Delayed Collision Detect Counter Register (CDCR)
CDCR is a 32-bit counter that indicates the number of delayed collisions on all lines from a start
of transmission. When the value in this register reaches H'FFFFFFFF, count-up is halted. The
counter value is cleared to 0 by a write to this register with any value.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COSDC[31:16]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
COSDC[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name
Value R/W Description
31 to 0 COSDC[31:0] All 0
R/W Delayed Collision Detect Count
These bits indicate the number of delayed collisions
on all lines from a start of transmission.
Rev. 1.00 Nov. 14, 2007 Page 412 of 1262
REJ09B0437-0100