SH7670 Datasheet, PDF (548/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC)
Bit
7 to 5
Bit Name
—
4
FECI_NI
3 to 1 —
0
FECI_EI
Initial
Value R/W Description
All 0 R
Reserved
These bits are always read as 0. The write value
should always be 0.
0
R/W "Invalid Descriptor (descriptor where FECD00_F0 is
0) Interrupt
Interrupt request for read end notification. When this
interrupt request is made, the FEC DMAC ends
processing and enters the IDLE state.
This bit is cleared to 0 by writing 1 to it. When 0 is
written to this bit, the current state is retained. This
interrupt is masked by the FECC_NIE bit of the
FECC. If this bit is set, the FEC DMAC is in the initial
state because descriptors ran dry. In this case,
replenish new descriptors and then restart the FEC
DMAC.
0: The "invalid descriptor processing end" interrupt is
not requested.
1: The "invalid descriptor processing end" interrupt is
requested.
All 0 R
Reserved
These bits are always read as 0. The write value
should always be 0.
0
R/W "Processing End" Interrupt Request
This interrupt notifies you that processing ended due
to the FECI_LI or FECI_NI interrupt source and the
FEC DMAC is now in the IDLE state.
This bit is cleared to 0 by writing 1 to it. When 0 is
written to this bit, the current state is retained. This
interrupt is masked by the FECC_EIE bit of the
FECC.
If this bit is set, the FEC DMAC is in the initial state
because descriptors ran dry. In this case, replenish
new descriptors and then restart the FEC DMAC.
0: The "processing end" interrupt is not requested.
1: The "processing end" interrupt is requested.
Rev. 1.00 Nov. 14, 2007 Page 522 of 1262
REJ09B0437-0100