SH7670 Datasheet, PDF (171/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 6 Interrupt Controller (INTC)
6.4.5 On-Chip Peripheral Module Interrupts
On-chip peripheral module interrupts are generated by the following on-chip peripheral modules:
• Direct memory access controller (DMAC)
• Ethernet controller (EtherC)
• Compare match timer (CMT)
• Bus state controller (BSC)
• Watchdog timer (WDT)
• DMAC with encryption/decryption and forward error correction core (A-DMAC)
• Stream interface (STIF)
• Host interface (HIF)
• Serial sound interface (SSI)
• SD host interface (SDHI)
• USB2.0 host/function module (USB)
• I²C bus interface 3 (IIC3)
• Serial communication interface with FIFO (SCIF)
As every source is assigned a different interrupt vector, the source does not need to be identified in
the exception service routine. A priority level in a range from 0 to 15 can be set for each module
by interrupt priority registers 06 to 16 (IPR06 to IPR16). The on-chip peripheral module interrupt
exception handling sets the I3 to I0 bits in SR to the priority level of the accepted on-chip
peripheral module interrupt.
Rev. 1.00 Nov. 14, 2007 Page 145 of 1262
REJ09B0437-0100