SH7670 Datasheet, PDF (435/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 12 Ethernet Controller (EtherC)
12.3.7 Receive Frame Length Register (RFLR)
RFLR is a 32-bit readable/writable register and it specifies the maximum frame length (in bytes)
that can be received by this LSI. The settings in this register must not be changed while the
receiving function is enabled.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
RFL[11:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 12 
Initial
Value
All 0
11 to 0 RFL[11:0] All 0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Receive Frame Length 11 to 0
The frame length described here refers to all fields
from the destination address up to and including the
CRC data. Frame contents from the destination
address up to and including the data are actually
transferred to memory. CRC data is not included in
the transfer.
When data that exceeds the specified value is
received, the part of the data that exceeds the
specified value is discarded.
H'000 to H'5EE: 1,518 bytes
H'5EF: 1,519 bytes
H'5F0: 1,520 bytes
:
:
H'7FF: 2,047 bytes
H'800 to H'FFF: 2,048 bytes
Rev. 1.00 Nov. 14, 2007 Page 409 of 1262
REJ09B0437-0100