SH7670 Datasheet, PDF (139/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 5 Exception Handling
5.2 Resets
5.2.1 Input/Output Pins
Table 5.5 shows the reset-related pin configuration.
Table 5.5 Pin Configuration
Pin Name
Symbol
Power-on reset RES
I/O
Input
Function
When this pin is driven low, this LSI shifts to the power-
on reset processing
5.2.2 Types of Reset
A reset is the highest-priority exception handling source. There are two kinds of reset, power-on
and manual. As shown in table 5.6, the CPU state is initialized in both a power-on reset and a
manual reset. The FPU state is initialized by a power-on reset, but not by a manual reset. On-chip
peripheral module registers are initialized by a power-on reset, but not by a manual reset.
Table 5.6 Reset States
Conditions for Transition to Reset State
Internal States
Type
WDT
RES H-UDI Command MRES Overflow CPU
On-Chip
WRCSR of
Peripheral
WDT, FRQCR of
Modules, I/O Port CPG
Power-on Low —
—
—
reset
High H-UDI reset assert —
—
command is set
Initialized Initialized
Initialized Initialized
Initialized
Initialized
High Command other —
than H-UDI reset
assert is set
Power-on Initialized Initialized
reset
Not initialized
Manual High Command other Low —
reset
than H-UDI reset
assert is set
Initialized Not initialized* Not initialized
High Command other
than H-UDI reset
assert is set
High
Manual
reset
Initialized Not initialized*
Not initialized
Note: * The BN bit in IBNR of the INTC is initialized.
Rev. 1.00 Nov. 14, 2007 Page 113 of 1262
REJ09B0437-0100