SH7670 Datasheet, PDF (421/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 12 Ethernet Controller (EtherC)
Section 12 Ethernet Controller (EtherC)
This LSI has an on-chip Ethernet controller (EtherC) conforming to the Ethernet or the IEEE802.3
MAC (Media Access Control) layer standard. Connecting a physical-layer LSI (PHY-LSI)
complying with this standard enables the Ethernet controller (EtherC) to perform transmission and
reception of Ethernet/IEEE802.3 frames. This LSI has one MAC layer interface.
The Ethernet controller is connected to the direct memory access controller for Ethernet controller
(E-DMAC) inside this LSI, and carries out high-speed data transfer to and from the memory.
Figure 12.1 shows a configuration of the EtherC.
12.1 Features
• Transmission and reception of Ethernet/IEEE802.3 frames
• Supports 10/100 Mbps receive/transfer
• Supports full-duplex and half-duplex modes
• Conforms to IEEE802.3u standard MII (Media Independent Interface)
• Magic Packet detection and Wake-On-LAN (WOL) signal output
• Conforms to IEEE802.3x flow control
Rev. 1.00 Nov. 14, 2007 Page 395 of 1262
REJ09B0437-0100