SH7670 Datasheet, PDF (362/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 8 Direct Memory Access Controller (DMAC)
(b) Burst Mode
In burst mode, once the DMAC obtains the bus mastership, it does not release the bus mastership
and continues to perform transfer until the transfer end condition is satisfied. In external request
mode with low level detection of the DREQ pin, however, when the DREQ pin is driven high, the
bus mastership is passed to another bus master after the DMAC transfer request that has already
been accepted ends, even if the transfer end conditions have not been satisfied.
Figure 8.11 shows DMA transfer timing in burst mode.
DREQ
Bus cycle
CPU
CPU CPU DMAC DMAC DMAC DMAC CPU
Read Write Read Write
CPU
Figure 8.11 DMA Transfer Example in Burst Mode
(Dual Address, DREQ Low Level Detection)
(3) Relationship between Request Modes and Bus Modes by DMA Transfer Category
Table 8.10 shows the relationship between request modes and bus modes by DMA transfer
category.
Rev. 1.00 Nov. 14, 2007 Page 336 of 1262
REJ09B0437-0100