SH7670 Datasheet, PDF (617/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 16 Serial Sound Interface (SSI)
Initial
Bit
Bit Name Value R/W Description
15
SCKD
0
14
SWSD
0
13
SCKP
0
R/W Serial Bit Clock Direction
0: Serial bit clock is input, slave mode.
1: Serial bit clock is output, master mode.
Note: Non-compression mode (CPEN = 0) permits only
the following settings: (SCKD, SWSD) = (0,0) and
(1,1). Other settings are prohibited.
R/W Serial WS Direction
0: Serial word select is input, slave mode.
1: Serial word select is output, master mode.
Note: Non-compression mode (CPEN = 0) permits only
the following settings: (SCKD, SWSD) = (0,0) and
(1,1). Other settings are prohibited.
R/W Serial Bit Clock Polarity
0: SSIWS and SSIDATA change at the SSISCK falling
edge (sampled at the SCK rising edge).
1: SSIWS and SSIDATA change at the SSISCK rising
edge (sampled at the SCK falling edge).
SCKP = 0
SCKP = 1
SSIDATA input sampling
timing at the time of
reception (TRMD = 0)
SSIDATA output change
timing at the time of
transmission (TRMD = 1)
SSISCK rising edge SSISCK falling edge
SSISCK falling edge SSISCK rising edge
SSIWS input sampling
timing at the time of slave
mode (SWSD = 0)
SSISCK rising edge
SSISCK falling edge
SSIWS output change
SSISCK falling edge
timing at the time of master
mode (SWSD = 1)
SSISCK rising edge
12
SWSP
0
R/W Serial WS Polarity
0: SSIWS is low for 1st channel, high for 2nd channel.
1: SSIWS is high for 1st channel, low for 2nd channel.
Rev. 1.00 Nov. 14, 2007 Page 591 of 1262
REJ09B0437-0100