SH7670 Datasheet, PDF (346/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 8 Direct Memory Access Controller (DMAC)
Table 8.4 DMARS Settings
Peripheral Module
USB_0
USB_1
SDHI
SSI_0
SSI_1
IIC3_0
SCIF_0
SCIF_1
SCIF_2
CMT_0
CMT_1
Setting Value for One
Channel ({MID, RID})
H'03
H'07
H'11
H'12
H'23
H'27
H'61
H'62
H'81
H'82
H'85
H'86
H'89
H'8A
H'FB
H'FF
MID
RID
B'000000
B'11
B'000001
B'11
B'000100
B'01
B'000100
B'10
B'001000
B'11
B'001001
B'11
B'011000
B'01
B'10
B'100000
B'10
B'01
B'100001
B'10
B'01
B'100010
B'10
B'01
B'111110
B'11
B'111111
B'11
Function


Transmit
Receive


Transmit
Receive
Receive
Transmit
Receive
Transmit
Receive
Transmit


When MID or RID other than the values listed in table 8.4 is set, the operation of this LSI is not
guaranteed. The transfer request from DMARS is valid only when the resource select bits
(RS[3:0]) in CHCR0 to CHCR7 have been set to B'1000. Otherwise, even if DMARS has been set,
the transfer request source is not accepted.
Rev. 1.00 Nov. 14, 2007 Page 320 of 1262
REJ09B0437-0100