SH7670 Datasheet, PDF (547/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC)
Bit
Bit Name
31 to 13 —
12
FECI_DI
11 to 9 —
8
FECI_LI
Initial
Value R/W
All 0 R
0
R/W
All 0 R
0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
"1 Descriptor Processing End" Interrupt Notification
Request
This interrupt notifies you that the FEC DMAC ended
1 descriptor processing and wrote back the
descriptor.
This bit is cleared to 0 by writing 1 to it. When 0 is
written to this bit, the current state is retained.
This interrupt is masked by the FECC_DIE bit of the
descriptor.
0: The "1 descriptor processing end" interrupt is not
requested.
1: The "1 descriptor processing end" interrupt is
requested.
Reserved
These bits are always read as 0. The write value
should always be 0.
"Last Descriptor (descriptor where FECD00_F2 is 1)
Processing End" Interrupt Notification Request
This interrupt notifies you that the FEC DMAC wrote
back the last descriptor and ended last descriptor
processing. The FEC DMAC enters the IDLE state
after it ended last descriptor processing.
This bit is cleared to 0 by writing 1 to it. When 0 is
written to this bit, the current state is retained. If this
bit is set, the FEC DMAC is in the initial state
because descriptors ran dry. In this case, replenish
new descriptors and then restart the FEC DMAC.
This interrupt is masked by the FECC_LIE bit of the
FECC.
0: The "last descriptor processing end" interrupt is
not requested.
1: The "last descriptor processing end" interrupt is
requested.
Rev. 1.00 Nov. 14, 2007 Page 521 of 1262
REJ09B0437-0100