SH7670 Datasheet, PDF (688/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 17 USB 2.0 Host/Function Module (USB)
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
BVAL BCLR FRDY —
DTLN[11:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W*² R/W*¹ R
R
R
R
R
R
R
R
R
R
R
R
R
R
Initial
Bit
Bit Name
Value R/W Description
15
BVAL
0
R/W*² Buffer Memory Valid Flag
This bit should be set to 1 when data has been
completely written to the FIFO buffer on the CPU
side for the pipe selected using the CURPIPE bits
(selected pipe).
0: Invalid
1: Writing ended
When the selected pipe is in the transmitting
direction, set this bit to 1 in the following cases.
Then, this module switches the FIFO buffer from the
CPU side to the SIE side, enabling transmission.
• To transmit a short packet, set this bit to 1 after
data has been written.
• To transmit a zero-length packet, set this bit to 1
before data is written to the FIFO buffer.
• Set this bit to 1 after the number of data bytes
has been written for the pipe in continuous
transfer mode, where the number is a natural
integer multiple of the maximum packet size and
less than the buffer size.
When the data of the maximum packet size has been
written for the pipe in continuous transfer mode, this
module sets this bit to 1 and switches the FIFO
buffer from the CPU side to the SIE side, enabling
transmission.
Writing 1 to this bit should be done while FRDY
indicates 1 (set by this module).
When the selected pipe is in the receiving direction,
do not set this bit to 1.
Rev. 1.00 Nov. 14, 2007 Page 662 of 1262
REJ09B0437-0100