SH7670 Datasheet, PDF (371/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 9 Clock Pulse Generator (CPG)
The clock pulse generator blocks function as follows:
(1) Crystal Oscillator
The crystal oscillator is an oscillation circuit in which the crystal resonator is connected to the
XTAL/EXTAL pin or USB_X1/USB_X2 pin. This can be used according to the clock operating
mode.
(2) Divider 1
Divider 1 divides the frequency of one of the three clocks: the clock from the crystal resonator or
the EXTAL pin, the clock from the CKIO pin, and the clock from the crystal resonator or the
USB_X1 pin. The division ratio depends on the clock operating mode.
(3) PLL Circuit
The PLL circuit multiplies the frequency of the output from divider 1 by 8 or 12. The
multiplication rate is set by the frequency control register. When this is done, the phase of the
rising edge of the internal clock is controlled so that it will agree with the phase of the rising edge
of the CKIO pin.
The input clock to be used depends on the clock operating mode. The clock operating mode is
specified using the MD_CK0 and MD_CK1 pins. For details on the clock operating mode, see
table 9.2.
(4) Divider 2
Divider 2 divides the frequency of output of the PLL circuit to generate an internal clock, a bus
clock, and a peripheral clock. The internal clock can be 1 or 1/2 times the output frequency of the
PLL circuit, and it should not be lower than the clock frequency on the CKIO pin. The peripheral
clock can be 1/4, 1/6, 1/8, or 1/12 times the output frequency of the PLL circuit, and it should not
be higher than the half of the clock frequency on the CKIO pin. The bus clock is automatically
determined by hardware at the division ratio against the output frequency of the PLL circuit so
that it will be 4 times the clock source (when clock mode = 0), 2 times (when clock mode = 1 or
3), or 1 times (when clock mode = 2).
(5) Clock Frequency Control Circuit
The clock frequency control circuit controls the clock frequency using the MD_CK0 and
MD_CK1 pins and the frequency control register (FRQCR).
Rev. 1.00 Nov. 14, 2007 Page 345 of 1262
REJ09B0437-0100