SH7670 Datasheet, PDF (522/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC)
Table 14.1 A-DMAC Submodules
Submodule Name
Channel for checksum
processing
Function
• DMA automatic processing based on descriptors
• Checksum operation
• Continuous execution of checksum
FEC channel
Arbiter
I-BUS interface
STIF interface
• DMA automatic processing based on descriptors
• XOR operation for any number of data items
• Arbitrates requests from the channel for checksum processing
and FEC channel.
• Channel arbitration mode is round robin scheduling.
• Conversion between I-BUS protocol and A-DMAC protocol
• Distribution of register R/W requests from the CPU to each
module
• Conversion between STIF protocol and A-DMAC protocol
• STIF0 is fixed at channel 0 for encryption/authentication.
• STIF1 is fixed at channel 1 for encryption/authentication.
Rev. 1.00 Nov. 14, 2007 Page 496 of 1262
REJ09B0437-0100