SH7670 Datasheet, PDF (1229/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 29 Electrical Characteristics
CKIO
A25 to A0
A12/A11^*1
Td1
Td2
Td3
Td4
Tc1
Tc2
Tc3
Tc4
Tde
t_AD1
t_AD1
t_AD1
Column
address
t_AD1
t_AD1
READ command
CSn
RD/WR
RAS
CAS
DQMxx
t_CSD1
t_RWD1
t_RASD1
t_CASD1
t_DQMD1
t_CSD1
t_RWD1
t_CASD1
t_DQMD1
D31 to D0
t_BSD
BS
t_RDS2
t_RDH2
t_BSD
t_RDS2 t_RDH2
CKE
DACKn
TENDn*²
t_DACD
(High)
t_DACD
Notes: 1. Address pin to be connected to A10 of SDRAM
2. The waveforms for DACKn and TENDn are produced when the active low state is specified.
Figure 29.25 Synchronous DRAM Burst-Read Bus Cycle (Equivalent to Four Read Cycles)
(Bank Active Mode: READ Command, Same Row Address, CAS Latency 2,
WTRCD = Zero Cycle)
Rev. 1.00 Nov. 14, 2007 Page 1203 of 1262
REJ09B0437-0100