SH7670 Datasheet, PDF (484/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC)
13.2.12 Receiving Method Control Register (RMCR)
RMCR is a 32-bit readable/writable register that specifies the control method for the RR bit in
EDRRR when a frame is received. This register must be set during the receiving-halt state.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
















Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0














 RNC
Initial Value: ⁰
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R R/W
Initial
Bit
Bit Name value R/W Description
31 to 1 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
0
RNC
0
R/W Receive Enable Control
0: When reception of one frame is completed, the E-
DMAC writes the receive status into the descriptor
and clears the RR bit in EDRRR
1: When reception of one frame is completed, the E-
DMAC writes the receive status into the descriptor,
reads the next descriptor, and prepares to receive
the next frame
Rev. 1.00 Nov. 14, 2007 Page 458 of 1262
REJ09B0437-0100