SH7670 Datasheet, PDF (452/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 12 Ethernet Controller (EtherC)
TE set
Transmission
halted
Reset
Idle
TE reset
HDPX
FDPX
Start of transmission
(preamble transmission)
Carrier
detection ^Carrier
non-detection
Carrier
detection
Retransfer
initiation
Collision
HDPX
Retransfer
processing*¹
Failure of 15
retransfer attempts
or collision
after 512-bit time
Carrier
detection
Carrier
non-detection
Collision
SFD
transmission
Error
Collision*²
FDPX
Error ^{Error detection}
notification
Error
Data
transmission
Collision*²
[Legend]
FDPX: Full Duplex
HDPX: Half Duplex
SFD: Start Frame Delimiter
Error
Normal transmission
CRC
transmission
Notes: 1. Transmission retry processing includes both jam transmission that depends on collision
detection and the adjustment of transmission intervals based on the back-off algorithm.
2. Transmission is retried only when data of 512 bits or less (including the preamble and
SFD) is transmitted. When a collision is detected during the transmission of data greater
than 512 bits, only jam is transmitted and transmission based on the back-off algorithm
is not retried.
Figure 12.2 EtherC Transmitter State Transitions
1. When the transmit enable (TE) bit is set, the transmitter enters the transmit idle state.
2. When a transmit request is issued by the transmit E-DMAC, the EtherC sends the preamble
after a transmission delay equivalent to the frame interval time. If full-duplex transfer is
selected, which does not require carrier detection, the preamble is sent as soon as a transmit
request is issued by the E-DMAC.
Rev. 1.00 Nov. 14, 2007 Page 426 of 1262
REJ09B0437-0100