SH7670 Datasheet, PDF (209/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 7 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
10, 9 BSZ[1:0] 11*
R/W Data Bus Width Specification
Specify the data bus widths of spaces.
00: Reserved (setting prohibited)
01: 8-bit size
10: 16-bit size
11: 32-bit size
For MPX-I/O, selects bus width by address
Notes:
1. The initial data bus width for areas 3 to 6
is specified by external pins. The BSZ[1:0]
bits settings in CS0BCR are ignored but
the bus width settings in CS1BCR to
CS7BCR can be modified.
2. If area 5 or area 6 is specified as PCMCIA
space, the bus width can be specified as
either 8 bits or 16 bits.
3. If area 3 is specified as SDRAM space,
the bus width can be specified as either 16
bits or 32 bits.
8 to 0 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Note: * CSnBCR samples the external pins (MD_BW) that specify the bus width at power-on
reset.
Rev. 1.00 Nov. 14, 2007 Page 183 of 1262
REJ09B0437-0100