SH7670 Datasheet, PDF (242/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 7 Bus State Controller (BSC)
Bit
27, 26
Bit Name

Initial
Value
All 0
25, 24 0P2R[1:0] 10
23, 22 
All 0
21, 20 0P3R[1:0] 11
19 to 0 
All 0
R/W Description
R Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Of the internal bus masters excluding the CPU (that is,
A-DMAC (including F-DMAC), E-DMAC, and DMAC),
set the internal bus master having the second highest
priority level.
00: No setting
01: A-DMAC (including F-DMAC)
10: E-DMAC
11: DMAC
R Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Of the internal bus masters excluding the CPU (that is,
A-DMAC (including F-DMAC), E-DMAC, and DMAC),
set the internal bus master having the third highest
priority level.
00: No setting
01: A-DMAC (including F-DMAC)
10: E-DMAC
11: DMAC
R Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.00 Nov. 14, 2007 Page 216 of 1262
REJ09B0437-0100