SH7670 Datasheet, PDF (1265/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 29 Electrical Characteristics
29.4.17 STIF Module Signal Timing (3)
(With Stream Input/Output Set Synchronized with STn_CLKIN Rise Time)
Table 29.23 STIF Module Signal Timing (3)
Conditions:
V_CC = V_CC (PLL) = DV12 = UV12 = 1.1 to 1.3 V, V_CCQ = DV33 = 3.1 to 3.5 V,
AV12 = 1.1 to 1.3 V, AV33 = 3.1 to 3.5 V,
V_SS = V_SS (PLL) = DG12 = UG12 = V_SSQ = DG33 = AG12 = AG33 = 0 V,
Ta = –20 to 70°C (regular specifications),
–40 to 85°C (wide temperature specifications)
Item
STn_SYC output delay time 1
STn_VLD output delay time 1
STn_REQ output delay time 1
STn_Dm output delay time 1
STn_SYC input setup time 1
STn_SYC input hold time 1
STn_VLD input setup time 1
STn_VLD input hold time 1
STn_REQ input setup time 1
STn_REQ input hold time 1
STn_Dm input setup time 1
STn_Dm input hold time 1
Symbol
t
STSD1
t_STVD1
t_STRD1
t
STDD1
t
STSS1
t
STSH1
t
STVS1
t_STVH1
T
STRS1
T_STRH1
t_STDS1
t_STDH1
Min.




4
6
4
6
4
6
4
6
Max.
Unit
11
ns
11
ns
11
ns
11
ns

ns

ns

ns

ns

ns

ns

ns

ns
Figure
29.70
Rev. 1.00 Nov. 14, 2007 Page 1239 of 1262
REJ09B0437-0100