SH7670 Datasheet, PDF (917/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 20 Host Interface (HIF)
20.4.8 HIF Data Register (HIFDATA)
HIFDATA is a 32-bit register used to hold data to be written to HIFRAM and data read from
HIFRAM for external device accesses. If HIFDATA is not used when accessing HIFRAM, it can
be used for data transfer between an external device connected to the HIF and the on-chip CPU.
HIFDATA can be read from and written to by the on-chip CPU. Access to HIFDATA by an
external device should be performed with HIFDATA specified by bits REG5 to REG0 in HIFIDX
and the HIFRS pin low.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
D[31:16]
Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
D[15:0]
Initial Value: ⁰
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
31 to 0
Initial
Bit Name Value
D[31:0] All 0
R/W
R/W
Description
32-bit data
20.4.9 HIF Boot Control Register (HIFBCR)
HIFBCR is a 32-bit register for exclusive control of an external device and the on-chip CPU
regarding access of HIFRAM. HIFBCR can be only read by the on-chip CPU. Access to HIFBCR
by an external device should be performed with HIFBCR specified by bits REG5 to REG0 in
HIFIDX and the HIFRS pin low.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
















Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0















AC
Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 0/1
R/W: R
R
R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 1.00 Nov. 14, 2007 Page 891 of 1262
REJ09B0437-0100