SH7670 Datasheet, PDF (734/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 17 USB 2.0 Host/Function Module (USB)
Bit
Bit Name
8
SQCLR
7
SQSET
Initial
Value
0
0
R/W
R/W*¹
R/W*¹
Description
Toggle Bit Clear
Specifies DATA0 as the expected value of the
sequence toggle bit for the next transaction during
the DCP transfer.
0: Invalid
1: Specifies DATA0.
This bit always indicates 0.
Do not set the SQCLR and SQSET bits to 1
simultaneously.
Set this bit to 1 while CSCTS is 0, PID is NAK, and
CURPIPE bits are not yet set.
Before setting this bit to 1 after modifying the PID
bits for the corresponding pipe from BUF to NAK,
check that CSSTS and PBUSY are 0.
However, if the PID bits have been modified to NAK
by this module, checking PBUSY through software
is not necessary.
Toggle Bit Set
Specifies DATA1 as the expected value of the
sequence toggle bit for the next transaction during
the DCP transfer.
0: Invalid
1: Specifies DATA1.
Do not set the SQCLR and SQSET bits to 1
simultaneously.
Set this bit to 1 while CSCTS is 0, PID is NAK, and
CURPIPE bits are not yet set.
Before setting this bit to 1 after modifying the PID
bits for the corresponding pipe from BUF to NAK,
check that CSSTS and PBUSY are 0.
However, if the PID bits have been modified to NAK
by this module, checking PBUSY through software
is not necessary.
Rev. 1.00 Nov. 14, 2007 Page 708 of 1262
REJ09B0437-0100