SH7670 Datasheet, PDF (912/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 20 Host Interface (HIF)
20.4.4 HIF Memory Control Register (HIFMCR)
HIFMCR is a 32-bit register used to control HIFRAM. HIFMCR can be only read by the on-chip
CPU. Access to HIFMCR by an external device should be performed with HIFMCR specified by
bits REG5 to REG0 in HIFIDX and the HIFRS pin low.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18














Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2







 LOCK 
WT

RD

Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R R/W* R R/W* R R/W* R
Note: * Changing the HIFRAM banks accessible from an external device by setting the BMD
and BSEL bits in HIFSCR does not affect the setting of this bit.
17 16


0
0
R
R
1
0
 AI/AD
0
0
R R/W*
Initial
Bit Bit Name Value
31 to 8 
All 0
7
LOCK
0
6

0
R/W
R
R/W*
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Lock
This bit is used to lock the access direction (read or write)
for consecutive access of HIFRAM by an external device
via HIFDATA. When this bit is set to 1, the values of the
RD and WT bits set at the same time are held until this bit
is next cleared to 0. When the RD bit and this bit are
simultaneously set to 1, consecutive read mode is
entered. When the WT bit and this bit are simultaneously
set to 1, consecutive write mode is entered. Both the RD
and WT bits should not be set to 1 simultaneously.
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 1.00 Nov. 14, 2007 Page 886 of 1262
REJ09B0437-0100