SH7670 Datasheet, PDF (17/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 14 DMAC That Works with Encryption/Decryption
and Forward Error Correction Core (A-DMAC) ...........................493
14.1 Overview........................................................................................................................... 493
14.1.1 Features............................................................................................................. 493
14.1.2 Overall Configuration of the A-DMAC............................................................ 494
14.1.3 Restrictions on the A-DMAC ........................................................................... 497
14.2 Register Descriptions........................................................................................................ 498
14.2.1 Channel [i] Processing Control Register (C[i]C) (i = 0, 1) ............................... 499
14.2.2 Channel [i] Processing Mode Register (C[i]M) (i = 0, 1) ................................. 502
14.2.3 Channel [i] Processing Interrupt Request Register (C[i]I) (i = 0, 1) ................. 503
14.2.4 Channel [i] Processing Descriptor Start Address Register
(C[i]DSA) (i = 0, 1)........................................................................................... 505
14.2.5 Channel [i] Processing Descriptor Current Address Register
(C[i]DCA) (i = 0, 1) .......................................................................................... 506
14.2.6 Channel [i] Processing Descriptor 0 Register (C[i]D0) [Control] (i = 0, 1)...... 507
14.2.7 Channel [i] Processing Descriptor 1 Register
(C[i]D1) [Source Address] (i = 0, 1) ................................................................. 513
14.2.8 Channel [i] Processing Descriptor 2 Register
(C[i]D2) [Destination Address] (i = 0, 1)......................................................... 514
14.2.9 Channel [i] Processing Descriptor 3 Register
(C[i]D3) [Data Length] (i = 0, 1) ...................................................................... 514
14.2.10 Channel [i] Processing Descriptor 4 Register
(C[i]D4) [Checksum Value Write Address] (i = 0, 1)....................................... 516
14.2.11 FEC DMAC Processing Control Register (FECC) ........................................... 516
14.2.12 FEC DMAC Processing Interrupt Request Register (FECI)............................. 520
14.2.13 FEC DMAC Processing Descriptor Start Address Register (FECDSA)........... 523
14.2.14 FEC DMAC Processing Descriptor Current Address Register (FECDCA) ..... 524
14.2.15 FEC DMAC Processing Descriptor 0 Register (FECD00) [Control] ............... 525
14.2.16 FEC DMAC Processing Descriptor 1 Register
(FECD01D0A) [Destination Address] .............................................................. 529
14.2.17 FEC DMAC Processing Descriptor 2 Register
(FECD02S0A) [Source 0 Address] ................................................................... 529
14.2.18 FEC DMAC Processing Descriptor 3 Register
(FECD03S1A) [Source 1 Address] ................................................................... 530
14.3 Functions........................................................................................................................... 531
14.3.1 DMAC Channel Function ................................................................................. 532
14.3.2 Checksum ......................................................................................................... 533
14.3.3 FEC Channel..................................................................................................... 533
14.3.4 FEC Operation .................................................................................................. 534
Rev. 1.00 Nov. 14, 2007 Page xvii of xxvi