SH7670 Datasheet, PDF (386/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 9 Clock Pulse Generator (CPG)
9.6.3 Note on Resonator
Since various characteristics related to the resonator are closely linked to the user’s board design,
thorough evaluation is necessary on the user’s part, using the resonator connection examples
shown in this section as a guide. As the parameters for the oscillation circuit will depend on the
floating capacitance of the resonator and the user board, the parameters should be determined in
consultation with the resonator manufacturer. The design must ensure that a voltage exceeding the
maximum rating is not applied to the resonator pin.
9.6.4 Note on Using a PLL Oscillation Circuit
In the PLLVcc and PLLVss connection pattern for the PLL, signal lines from the board power
supply pins must be as short as possible and pattern width must be as wide as possible to reduce
inductive interference.
In clock operating mode 2 or 3, the EXTAL pin is pulled up and the XTAL pin is left open.
Since the analog power supply pins of the PLL are sensitive to the noise, the system may
malfunction due to inductive interference at the other power supply pins. To prevent such
malfunction, the analog power supply pin Vcc and digital power supply pin PVcc should not
supply the same resources on the board if at all possible.
Signal lines prohibited
PLLVcc
Power supply
Vcc
PLLVss
Vss
Figure 9.4 Note on Using a PLL Oscillation Circuit
Rev. 1.00 Nov. 14, 2007 Page 360 of 1262
REJ09B0437-0100