SH7670 Datasheet, PDF (526/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC)
Bit
Bit Name
8
C[i]C_VLD
7 to 5 —
4
C[i]C_EIE
3 to 1 —
Initial
Value R/W
0
R/W
All 0 R
0
R/W
All 0 R
Description
Variable-Length Descriptor Control Flag
0: Fixed-length descriptor (32 bytes)
1: Variable-length descriptor (16/32 bytes)
The A-DMAC channel uses the 32-byte fixed length
structure or 16/32-byte variable-length structure. If
this bit is set to 0 to define the descriptor as the
fixed-length, the descriptor is always read as 32
bytes. If this bit is set to 1 to define the descriptor as
the variable-length, the first 16 bytes are read, and if
r_cid4/r_cid5/r_cid6/r_cid7 information is required,
the remaining 16 bytes are read according to the
contents of r_cidm/r_cihm.
Reserved
These bits are always read as 0. The write value
should always be 0.
"Processing End" Interrupt Request Enable
When processing ends, specifies whether to enable
or disable the "processing end" interrupt request.
0: Disables the "processing end" interrupt request.
1: Enables the "processing end" interrupt request.
A-DMAC channel [i] processing end means fetching
of depleted descriptors (invalid descriptors
(descriptors where C[i]F0 is set to 0)).
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.00 Nov. 14, 2007 Page 500 of 1262
REJ09B0437-0100