SH7670 Datasheet, PDF (292/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 7 Bus State Controller (BSC)
(10) Power-Down Mode
If the PDOWN bit in SDCR is set to 1, the SDRAM is placed in power-down mode by bringing
the CKE signal to the low level in the non-access cycle. This power-down mode can effectively
lower the power consumption in the non-access cycle. However, please note that if an access
occurs in power-down mode, a cycle of overhead occurs because a cycle is needed to assert the
CKE in order to cancel the power-down mode.
Figure 7.27 shows the access timing in power-down mode.
Power-down Tnop
Tr
CKIO
CKE
Tc1
Td1
Tde
Tap Power-down
A25 to A0
A12/A11*¹
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0
BS
DACKn*²
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 7.27 Power-Down Mode Access Timing
Rev. 1.00 Nov. 14, 2007 Page 266 of 1262
REJ09B0437-0100