SH7670 Datasheet, PDF (211/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 7 Bus State Controller (BSC)
Bit
19, 18
Bit Name

17, 16 
15 to 13 
12, 11 SW[1:0]
Initial
Value
All 0
All 0
All 0
00
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Reserved
Set this bit to 0 when the interface for normal space or
SRAM with byte selection is used.
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Number of Delay Cycles from Address, CS0 Assertion
to RD, WEn Assertion
Specify the number of delay cycles from address and
CS0 assertion to RD and WEn assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Rev. 1.00 Nov. 14, 2007 Page 185 of 1262
REJ09B0437-0100