SH7670 Datasheet, PDF (98/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 2 CPU
2.5 Processing States
The CPU has five processing states: reset, exception handling, bus-released, program execution,
and power-down. Figure 2.6 shows the transitions between the states.
Power-on reset from any state
Manual reset from any state
Power-on reset state
Manual reset state
Reset canceled
Interrupt source or
DMA address error occurs
Exception
handling state
Bus request
cleared
Exception
handling
Bus request _source
generated _occurs
Bus-released state
Bus request
cleared
Exception
handling
ends
Bus request
generated
Bus request
generated
Bus request
cleared
Program execution state
STBY bit cleared
for SLEEP
instruction
Reset state
NMI interrupt or
IRQ interrupt occurs
STBY and DEEP bits set
for SLEEP
instruction
Sleep mode
Software standby mode
Power-down state
Figure 2.6 Transitions between Processing States
Rev. 1.00 Nov. 14, 2007 Page 72 of 1262
REJ09B0437-0100