SH7670 Datasheet, PDF (1076/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 24 I/O Ports
24.4.2 Port D Data Register L (PDDRL)
PDDRL is a 16-bit readable/writable register that stores port D data. Bits PD7DR to PD0DR
correspond to pins PD7 to PD0, respectively (description of the other functions are omitted).
If a pin is set to the general output function, the pin will output the value written to the
corresponding bit in PDDRL, and the register value is read from PDDRL regardless of the state of
the pin.
If a pin is set to the general input function, the pin state, not the register value, will be returned if
PDDRL is read. Also, if a value is written to PDDRL, although the value will actually be written,
it will have no influence on the state of the pin.Table 24.4 summarizes the PDDRL read/write
operations.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
DR DR
DR DR
DR DR
DR DR
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit
Name
15 to 8 —
Initial
Value R/W
All 0 R
7
PD7DR 0
R/W
6
PD6DR 0
R/W
5
PD5DR 0
R/W
4
PD4DR 0
R/W
3
PD3DR 0
R/W
2
PD2DR 0
R/W
1
PD1DR 0
R/W
0
PD0DR 0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
See table 24.4.
Rev. 1.00 Nov. 14, 2007 Page 1050 of 1262
REJ09B0437-0100