SH7670 Datasheet, PDF (830/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 17 USB 2.0 Host/Function Module (USB)
Table 17.26 Packet Reception and Buffer Memory Clearing Processing
Buffer Status
When Packet is Received
Buffer full
Zero-length packet reception
Normal short packet reception
Transaction count ended
Register Setting
DCLRM = 0
DCLRM = 1
BFRE = 0
BFRE = 1
BFRE = 0
BFRE = 1
Doesn't need Doesn't need Doesn't need Doesn't need
to be cleared to be cleared to be cleared to be cleared
Needs to be Needs to be Doesn't need Doesn't need
cleared
cleared
to be cleared to be cleared
Doesn't need Needs to be Doesn't need Doesn't need
to be cleared cleared
to be cleared to be cleared
Doesn't need Needs to be Doesn't need Doesn't need
to be cleared cleared
to be cleared to be cleared
17.4.5 Control Transfers (DCP)
Data transfers of the data stage of control transfers are done using the default control pipe (DCP).
The DCP buffer memory is a 256-byte single buffer, and is a fixed area that is shared for both
control reading and control writing. The buffer memory can be accessed through the CFIFO port.
(1) Control Transfers when the Host Controller Function is Selected
(a) Setup Stage
USQREQ, USBVAL, USBINDX, and USBLENG are the registers that are used to transmit a USB
request for setup transactions. Writing setup packet data to the registers and writing 1 to the
SUREQ bit in DCPCTR transmits the specified data for setup transactions. Upon completion of
transactions, the SUREQ bit is cleared to 0. The above USB request registers should not be
modified while SUREQ = 1. The device address for setup transactions is specified using the
DEVSEL bits in DCPMAXP.
When the data for setup transactions has been sent, a SIGN or SACK interrupt request is generated
according to the response received from the peripheral device (SIGN1 or SACK bits in INTSTS1),
by means of which the result of the setup transactions can be confirmed.
A data packet of DATA0 (USB request) is transmitted as the data packet for the setup transactions
regardless of the setting of the SQMON bit in DCPCTR.
Rev. 1.00 Nov. 14, 2007 Page 804 of 1262
REJ09B0437-0100