SH7670 Datasheet, PDF (913/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 20 Host Interface (HIF)
Initial
Bit Bit Name Value R/W Description
5
WT
0
R/W* Write
When this bit is set to 1, the HIFDATA value is written to
the HIFRAM position corresponding to HIFADR.
If this bit and the LOCK bit are set to 1 simultaneously,
HIFRAM consecutive write mode is entered, and high-
speed data transfer becomes possible. This mode is
maintained until this bit is next cleared to 0, or until the
LOCK bit is cleared to 0.
If the LOCK bit is not simultaneously set to 1 with this bit,
writing to HIFRAM is performed only once. Thereafter, the
value of this bit is automatically cleared to 0.
4

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
3
RD
0
R/W* Read
When this bit is set to 1, the HIFRAM data corresponding
to HIFADR is fetched to HIFDATA.
If this bit and the LOCK bit are set to 1 simultaneously,
HIFRAM consecutive read mode is entered, and high-
speed data transfer becomes possible. This mode is
maintained until this bit is next cleared to 0, or until the
LOCK bit is cleared to 0.
If the LOCK bit is not simultaneously set to 1 with this bit,
reading of HIFRAM is performed only once. Thereafter,
the value of this bit is automatically cleared to 0.
2, 1 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
0
AI/AD
0
R/W* Address Auto-Increment/Decrement
This bit is valid only when the LOCK bit is 1. The value of
HIFADR is automatically incremented by 4 or
decremented by 4 according to the setting of this bit each
time reading or writing of HIFRAM is performed.
0: Auto-increment mode (+4)
1: Auto-decrement mode (−4)
Note: * Changing the HIFRAM banks accessible from an external device by setting the BMD
and BSEL bits in HIFSCR does not affect the setting of this bit.
Rev. 1.00 Nov. 14, 2007 Page 887 of 1262
REJ09B0437-0100