SH7670 Datasheet, PDF (573/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

• STIF lock control register (STLKCR_1)
• STIF debugging status register (STDBGR_1)
Section 15 Stream Interface (STIF)
15.3.1 STIF Mode Select Register (STMDR)
STMDR is a 32-bit register that selects operating mode, clock source, etc. of the on-chip STIF
module. STMDR is initialized to H'00000000 by a power-on reset.
Bit
31 to 15
14
13
12
Initial
Bit Name Value R/W

All 0 R
LSBSEL 0
R/W
EDGSEL 0
R/W
CLKSEL 0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Selects MSB first or LSB first in serial mode.
0: MSB-first data input/output
1: LSB-first data input/output
Selects input/output timing of STn_REQ, STn_SYC,
STn_VLD, and STn_D[7:0].
0: Output and sampled at the rising edge of the
synchronizing clock
1: Output and sampled at the falling edge of the
synchronizing clock
The synchronizing clock is defined by the CLKSEL and
CKFRSEL[3:0] bits in this register.
Selects synchronizing clock for stream transmit mode
0: STn_SYC, STn_VLD, and STn_D[7:0] are output in
synchronization with ST_CLKOUT.
STn_REQ is sampled in synchronization with
ST_CLKOUT
1: STn_SYC, STn_VLD, and STn_D[7:0] are output in
synchronization with STn_CLKIN.
STn_REQ is sampled in synchronization with
STn_CLKIN.
Rev. 1.00 Nov. 14, 2007 Page 547 of 1262
REJ09B0437-0100