SH7670 Datasheet, PDF (1112/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 26 High-Performance User Debugging Interface (H-UDI)
26.3.2 Instruction Register (SDIR)
SDIR is a 16-bit read-only register. It is initialized by TRST assertion or in the TAP test-logic-
reset state, and can be written to by the H-UDI irrespective of the CPU mode. Operation is not
guaranteed if a reserved command is set in this register. The initial value is H'EFFD.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TI[7:0]
-
-
-
-
-
-
-
-
Initial value: 1* 1* 1* 0* 1* 1* 1* 1* 1
1
1
1
1
1
0
1
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Note: * The initial value of the TI[7:0] bits is a reserved value. When setting a command, the TI[7:0] bits must be set to another value.
Bit
15 to 8
7 to 2
1
0
Bit Name Initial Value
TI[7:0]
11101111*

All 1

0

1
R/W Description
R
Test Instruction
The H-UDI instruction is transferred to SDIR by a
serial input from TDI.
For commands, see table 26.3.
R
Reserved
These bits are always read as 1.
R
Reserved
This bit is always read as 0.
R
Reserved
This bit is always read as 1.
Table 26.3 H-UDI Commands
Bits 15 to 8
TI7 TI6 TI5 TI4 TI3 TI2 TI1 TI0 Description
0
1
1
0
—
—
—
—
H-UDI reset negate
0
1
1
1
—
—
—
—
H-UDI reset assert
1
0
0
1
1
1
0
0
TDO change timing switch
1
0
1
1
—
—
—
—
H-UDI interrupt
1
1
1
1
—
—
—
—
BYPASS mode
Other than above
Reserved
Rev. 1.00 Nov. 14, 2007 Page 1086 of 1262
REJ09B0437-0100