SH7670 Datasheet, PDF (899/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 19 I²C Bus Interface 3 (IIC3)
19.7 Usage Notes
19.7.1
Notes on Working in Multi-master Mode
When working in multi-master mode, if the setting for the transfer route of the LSI (CKS3 to
CKS0 in ICCR1) is lower than that for any other master, an SCL with an unexpected width may
be output occasionally.
The transfer rate that is set here must be at least 1/1.8 times the highest transfer rate of the other
masters.
19.7.2
Notes on Working in Master Receive Mode
If the ICDRR is read near the falling edge of the eighth clock, no receive data may be captured.
If RCVD = 1 is set near the falling edge of the eighth clock when the receive buffer is full, no stop
conditions may be issued.
Use either of the following methods.
1. In master receive mode, reading the ICDRR should be performed before the falling edge of the
eighth is detected.
2. In master receive mode, RCVD = 1 should be set so that processing proceeds on a per-byte
basis.
19.7.3 Notes on Setting ACKBT in Master Receive Mode
When working in master receive mode, the ACKBT should be set before the eighth SCL in the
final data being transferred continuously starts falling. Otherwise, the slave’s sending device
might overrun.
Rev. 1.00 Nov. 14, 2007 Page 873 of 1262
REJ09B0437-0100