SH7670 Datasheet, PDF (1254/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 29 Electrical Characteristics
29.4.12 HIF Module Signal Timing
Table 29.18 HIF Module Signal Timing
Conditions:
V_CC = V_CC (PLL) = DV12 = UV12 = 1.1 to 1.3 V, V_CCQ = DV33 = 3.1 to 3.5 V,
AV12 = 1.1 to 1.3 V, AV33 = 3.1 to 3.5 V,
V_SS = V_SS (PLL) = DG12 = UG12 = V_SSQ = DG33 = AG12 = AG33 = 0 V,
Ta = –20 to 70°C (regular specifications),
–40 to 85°C (wide temperature specifications)
Item
Symbol
Min.
Max.
Unit Figure
Read bus cycle time
t
HIFCYCR
5.0

t
29.55
pcyc
Write bus cycle time
t_HIFCYCW
5.0

t_pcyc
Read low width (in reading)
t
3.0

t
HIFWRL
pcyc
Write low width (in writing)
t_HIFWWL
3.0

t_pcyc
Read/write high width
t_HIFWRWH
2.0

t_pcyc
Read data delay time
t_HIFRDD

2 × t_pcyc + 16 ns
Read data hold time
t
0

ns
HIFRDH
Write data setup time
t
t + 10 
ns
HIFWDS
pcyc
Write data hold time
t
10

ns
HIFWDH
HIFINT output delay time
t
HIFITD

20
ns
29.56
HIFRDY output delay time
t_HIFRYD

20
t_pcyc
29.57
HIFDREQ output delay time
t
HIFDQD

20
ns
29.56
HIF pin enable delay time
t_HIFEBD

20
ns
29.57
HIF pin disable delay time
t_HIFDBD

20
ns
29.57
Notes: 1. t indicates the peripheral clock (Pφ) cycle.
pcyc
2. The t period is specified as the overlap between the LOW period of the HIFCS
HIFWRL
signal and the LOW period of the HIFRD signal.
3. The t_HIFWWL period is specified as the overlap between the LOW period of the HIFCS
signal and the LOW period of the HIFWR signal.
4.
The
t
HIFWRWH
(min)
is
equal
to
2
×
tpcyc
+
5
ns
when
writing
into
the
HIF
index
register
(HIFIDX) is followed by reading from the registers REG5 to REG0.
Rev. 1.00 Nov. 14, 2007 Page 1228 of 1262
REJ09B0437-0100