SH7670 Datasheet, PDF (908/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 20 Host Interface (HIF)
20.4.2 HIF General Status Register (HIFGSR)
HIFGSR is a 32-bit register, which can be freely used for handshaking between an external device
connected to the HIF and the software of this LSI. HIFGSR can be read from and written to by the
on-chip CPU. Access to HIFGSR by an external device should be performed with HIFGSR
specified by bits REG5 to REG0 in HIFIDX and the HIFRS pin low.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
















Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15
Initial Value: 0
R/W: R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
7
STATUS[15:0]
0
0
R/W R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Initial
Bit
Bit Name
Value R/W Description
31 to 16 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
15 to 0 STATUS[15:0] All 0
R/W General Status
This register can be read from and written to by an
external device connected to the HIF, and by the on-
chip CPU. These bits are initialized only at a power-
on reset.
Rev. 1.00 Nov. 14, 2007 Page 882 of 1262
REJ09B0437-0100