SH7670 Datasheet, PDF (151/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 5 Exception Handling
instruction are handled as an undefined code; when such an instruction is placed anywhere other
than immediately after a delayed branch instruction (i.e., in a delay slot), general illegal instruction
exception handling starts if the instruction is decoded.
The CPU handles general illegal instruction exception in the same way as slot illegal instruction
exception. Unlike processing of slot illegal instruction exception, however, the program counter
value stored is the start address of the undefined code.
5.6.5 Integer Division Instructions
When an integer division instruction performs division by zero or the result of integer division
overflows, integer division instruction exception handling starts. The instructions that may become
the source of division-by-zero exception are DIVU and DIVS. The only source instruction of
overflow exception is DIVS, and overflow exception occurs only when the negative maximum
value is divided by −1. The CPU operates as follows:
1. The exception service routine start address which corresponds to the integer division
instruction exception that occurred is fetched from the exception handling vector table.
2. The status register (SR) is saved to the stack.
3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
integer division instruction at which the exception occurred.
4. After jumping to the exception service routine start address fetched from the exception
handling vector table, program execution starts. The jump that occurs is not a delayed branch.
Rev. 1.00 Nov. 14, 2007 Page 125 of 1262
REJ09B0437-0100