SH7670 Datasheet, PDF (485/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC)
13.2.13 E-DMAC Operation Control Register (EDOCR)
EDOCR is a 32-bit readable/writable register that specifies the control methods used in E-DMAC
operation.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
















Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0











 FEC AEC EDH 
Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R R/W R/W R/W R
Initial
Bit
Bit Name value R/W Description
31 to 4 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
3
FEC
0
R/W FIFO Error Control
Specifies E-DMAC operation when transmit FIFO
underflow or receive FIFO overflow occurs.
0: E-DMAC operation continues when underflow or
overflow occurs
1: E-DMAC operation halts when underflow or
overflow occurs
2
AEC
0
R/W Address Error Control
Indicates detection of an illegal memory address in an
attempted E-DMAC transfer.
0: Illegal memory address not detected (normal
operation)
1: E-DMAC stops its operation due to illegal memory
address detection
Note: To resume the operation, set the E-DMAC again
after software reset by means of the SWR bit in
EDMR.
Rev. 1.00 Nov. 14, 2007 Page 459 of 1262
REJ09B0437-0100