SH7670 Datasheet, PDF (332/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 8 Direct Memory Access Controller (DMAC)
Initial
Bit
Bit Name Value R/W Descriptions
18
HIE
0
R/W Half-End Interrupt Enable
Specifies whether to issue an interrupt request to the
CPU when the transfer count reaches half of the
DMATCR value that was specified before transfer
starts.
When the HIE bit is set to 1, the DMAC requests an
interrupt to the CPU when the HE bit becomes 1.
0: Disables an interrupt to be issued when DMATCR
= (DMATCR set before transfer starts)/2.
1: Enables an interrupt to be issued when DMATCR
= (DMATCR set before transfer starts)/2.
17
AM
0
R/W Acknowledge Mode
Specifies whether DACK is output in data read cycle or
in data write cycle in dual address mode.
In single address mode, DACK is always output
regardless of the specification by this bit.
This bit is valid only in CHCR_0 and CHCR_1. This bit
is reserved in CHCR_2 to CHCR_7; it is always read
as 0 and the write value should always be 0.
0: DACK output in read cycle (dual address mode)
1: DACK output in write cycle (dual address mode)
16
AL
0
R/W Acknowledge Level
Specifies the DACK (acknowledge) signal output is
high active or low active.
This bit is valid only in CHCR_0 and CHCR_1. This bit
is reserved in CHCR_2 to CHCR_7; it is always read
as 0 and the write value should always be 0.
0: Low-active output from DACK
1: High-active output from DACK
Rev. 1.00 Nov. 14, 2007 Page 306 of 1262
REJ09B0437-0100