SH7670 Datasheet, PDF (1257/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 29 Electrical Characteristics
29.4.13 EtherC Module Signal Timing
Table 29.19 EtherC Module Signal Timing
Conditions:
V_CC = V_CC (PLL) = DV12 = UV12 = 1.1 to 1.3 V, V_CCQ = DV33 = 3.1 to 3.5 V,
AV12 = 1.1 to 1.3 V, AV33 = 3.1 to 3.5 V,
V_SS = V_SS (PLL) = DG12 = UG12 = V_SSQ = DG33 = AG12 = AG33 = 0 V,
Ta = –20 to 70°C (regular specifications),
–40 to 85°C (wide temperature specifications)
Item
Symbol
Min.
Max.
Unit
Figure
TX-CLK cycle time
t
40

ns

Tcyc
TX-EN output delay time
t_TENd
1
20
ns
29.58
MII_TXD[3:0] output delay time t
MTDd
1
20
ns
CRS setup time
t_CRSs
10

ns
CRS hold time
t_CRSh
10

ns
COL setup time
t_COLs
10

ns
29.59
COL hold time
t
COLh
10

ns
RX-CLK cycle time
t
40

ns

Rcyc
RX-DV setup time
t
10

ns
29.60
RDVs
RX-DV hold time
t
RDVh
10

ns
MII_RXD[3:0] setup time
t_MRDs
10

ns
MII_RXD[3:0] hold time
t
MRDh
10

ns
RX-ER setup time
t_RERs
10

ns
29.61
RX-ER hold time
t_RERh
10

ns
MDIO setup time
t_MDIOs
10

ns
29.62
MDIO hold time
t
MDIOh
10

ns
MDIO output data hold time*
t
MDIOdh
5
18
ns
29.63
WOL output delay time
t
1
20
ns
29.64
WOLd
EXOUT output delay time
t
1
EXOUTd
20
ns
29.65
Note: * Operate the internal register (PIR) in PHY block to meet the requirement of this
specification.
Rev. 1.00 Nov. 14, 2007 Page 1231 of 1262
REJ09B0437-0100