SH7670 Datasheet, PDF (142/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 5 Exception Handling
5.2.4 Manual Reset
(1) Manual Reset by Means of WDT
When a manual reset is set to occur in the WDT’s watchdog timer mode, if the WDT’s WTCNT
overflows, the manual reset state is established. In the manual reset state, the internal state of the
CPU is initialized, but the registers in on-chip peripheral modules are not initialized.
When manual reset exception handling is started, the CPU operates as follows.
1. The initial value (execution start address) of the program counter (PC) is fetched from the
exception handling vector table.
2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table.
3. The vector base register (VBR) is cleared to H'00000000, the interrupt mask level bits (I3 to
I0) of the status register (SR) are initialized to H'F (B'1111), and the BO and CS bits are
initialized. The BN bit in IBNR of the INTC is also initialized to 0.
4. The values fetched from the exception handling vector table are set in the PC and SP, and the
program begins executing.
When a manual reset is generated, the bus cycle is retained, but if a manual reset occurs while the
bus is released or during DMAC burst transfer, manual reset exception handling will be deferred
until the CPU acquires the bus. However, if the interval from generation of the manual reset until
the end of the bus cycle is equal to or longer than the fixed internal manual reset interval cycles,
the internal manual reset source is ignored instead of being deferred, and manual reset exception
handling is not executed. The FPU and other modules are not initialized.
Rev. 1.00 Nov. 14, 2007 Page 116 of 1262
REJ09B0437-0100