SH7670 Datasheet, PDF (620/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 16 Serial Sound Interface (SSI)
Bit
6 to 4
Bit Name
CKDV[2:0]
Initial
Value
000
3
MUEN
0
2

0
1
TRMD
0
0
EN
0
R/W
R/W
R/W
R
R/W
R/W
Description
Serial Oversampling Clock Division Ratio
Sets the ratio between oversampling clock* and the
serial bit clock. When the SCKD bit is 0, the setting of
these bits is ignored. The serial bit clock is used in the
shift register and is supplied from the SSISCK pin.
000: Serial bit clock frequency = Oversampling clock Frequency/1
001: Serial bit clock frequency = Oversampling clock frequency/2
010: Serial bit clock frequency = Oversampling clock frequency/4
011: Serial bit clock frequency = Oversampling clock frequency/8
100: Serial bit clock frequency = Oversampling clock frequency/16
101: Serial bit clock frequency = Oversampling clock frequency/6
110: Serial bit clock frequency = Oversampling clock frequency/12
111: Setting prohibited
Note: * An oversampling clock is selected by the
SCSR_0/SCSR_1 setting.
Mute Enable
0: Module is not muted.
1: Module is muted.
Reserved
The read value is undefined. The write value should
always be 0.
Transmit/Receive Mode Select
0: Module is in receive mode.
1: Module is in transmit mode.
SSI Module Enable
0: Module is disabled.
1: Module is enabled.
Rev. 1.00 Nov. 14, 2007 Page 594 of 1262
REJ09B0437-0100