SH7670 Datasheet, PDF (793/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 17 USB 2.0 Host/Function Module (USB)
(b) When the BRDYM bit is 0 and the BFRE bit is 1
With these settings, this module generates the BRDY interrupt on completion of reading all the
data for a single transfer using the pipe in the receiving direction, and sets 1 to the PIPEBRDY bit
corresponding to the pertinent pipe.
On any of the following conditions, this module determines that the last data for a single transfer
has been received.
• When a short packet including a zero-length packet is received.
• When the transaction counter register (TRNCNT bits) is used and the number of packets
specified by the TRNCNT bits are completely received.
When the pertinent data is completely read out after any of the above determination conditions has
been satisfied, this module determines that all the data for a single transfer has been completely
read out.
When a zero-length packet is received when the FIFO buffer is empty, this module determines that
all the data for a single transfer has been completely read out upon passing the zero-length packet
data to the CPU. In this case, to start the next transfer, write 1 to the BCLR bit in the
corresponding FIFOCTR register through software.
With these settings, this module does not detect the BRDY interrupt for the pipe in the
transmitting direction.
The PIPEBRDY interrupt status of the pertinent pipe can be cleared to 0 by writing 0 to the
corresponding PIPEBRDY interrupt status bit through software. In this case, 1s should be written
to the PIPEBRDY interrupt status bits for the other pipes.
In this mode, the BFRE bit setting should not be modified until all the data for a single transfer has
been processed. When it is necessary to modify the BFRE bit before completion of processing, all
the FIFO buffers for the pertinent pipe should be cleared using the ACLRM bit.
Rev. 1.00 Nov. 14, 2007 Page 767 of 1262
REJ09B0437-0100