SH7670 Datasheet, PDF (93/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 2 CPU
2.4.8 Floating-Point Operation Instructions
Table 2.17 Floating-Point Operation Instructions
Instruction
FABS FRn
FABS DRn
FADD FRm, FRn
FADD DRm, DRn
FCMP/EQ FRm, FRn
FCMP/EQ DRm, DRn
FCMP/GT FRm, FRn
FCMP/GT DRm, DRn
FCNVDS DRm, FPUL
FCNVSD FPUL, DRn
FDIV
FRm, FRn
FDIV
DRm, DRn
FLDI0 FRn
FLDI1 FRn
FLDS FRm, FPUL
FLOAT FPUL,FRn
FLOAT FPUL,DRn
FMAC FR0,FRm,FRn
FMOV
FMOV
FRm, FRn
DRm, DRn
Instruction Code
1111nnnn01011101
1111nnn001011101
1111nnnnmmmm0000
1111nnn0mmm00000
1111nnnnmmmm0100
1111nnn0mmm00100
1111nnnnmmmm0101
1111nnn0mmm00101
1111mmm010111101
1111nnn010101101
1111nnnnmmmm0011
1111nnn0mmm00011
1111nnnn10001101
1111nnnn10011101
1111mmmm00011101
1111nnnn00101101
1111nnn000101101
1111nnnnmmmm1110
1111nnnnmmmm1100
1111nnn0mmm01100
Compatibility
Operation
Execu-
tion
Cycles T Bit
SH2E SH4
SH-2A/
SH2A-
FPU
|FRn| → FRn
1

Yes Yes Yes
|DRn| → DRn
1

Yes Yes
FRn + FRm → FRn
1

Yes Yes Yes
DRn + DRm → DRn
6

Yes Yes
(FRn = FRm)? 1:0 → T 1
Compa- Yes Yes Yes
rison
result
(DRn = DRm)? 1:0 → T 2
Compa-
rison
result
Yes Yes
(FRn > FRm)? 1:0 → T 1
Compa Yes Yes Yes
-rison
result
(DRn > DRm)? 1:0 → T 2
Compa-
rison
result
Yes Yes
(float) DRm → FPUL 2

Yes Yes
(double) FPUL → DRn 2

Yes Yes
FRn/FRm → FRn
10

Yes Yes Yes
DRn/DRm → DRn
23

Yes Yes
0 × 00000000 → FRn 1

Yes Yes Yes
0 × 3F800000 → FRn 1

Yes Yes Yes
FRm → FPUL
1

Yes Yes Yes
(float)FPUL → FRn
1

Yes Yes Yes
(double)FPUL → DRn 2

Yes Yes
FR0 × FRm+FRn →
1
FRn

Yes Yes Yes
FRm → FRn
1

Yes Yes Yes
DRm → DRn
2

Yes Yes
Rev. 1.00 Nov. 14, 2007 Page 67 of 1262
REJ09B0437-0100