SH7670 Datasheet, PDF (553/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC)
Bit
11 to 8
7 to 4
Bit Name
FECD00_SO[3:0]
FECD00_SN[3:0]
Initial
Value R/W Description
All 0 R/W These bits function when the source is read.
FECD00_SO3:
Data swap in two-byte units (longword swap in
word units)
0: As-is
1: Swap
FECD00_SO2:
Data swap in one-byte units (word swap in byte
units)
0: As-is
1: Swap
FECD00_SO1:
Inver,sion of bit 1 at address when one or two
bytes are accessed
0: As-is
1: Inversion
FECD00_SO0:
Inversion of bit 0 at address when one byte is
accessed
0: As-is
1: Inversion
FECD00_SO1 and FECD00_SO0 function for
endian adjustment. Note that if an endian different
from the endian of this LSI is used, up to three
different addresses are accessed from the address
where the start and end addresses are specified
when an area is allocated.
All 0 R/W Number of Source Addresses
Specify the number of source addresses subject to
FEC operation.
0000: The number of source addresses is 1.
0001: The number of source addresses is 2.
Others: Reserved (setting prohibited)
Rev. 1.00 Nov. 14, 2007 Page 527 of 1262
REJ09B0437-0100