SH7670 Datasheet, PDF (153/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 5 Exception Handling
5.7 When Exception Sources Are Not Accepted
When an address error, FPU exception, register bank error (overflow), or interrupt is generated
immediately after a delayed branch instruction, it is sometimes not accepted immediately but
stored instead, as shown in table 5.11. When this happens, it will be accepted when an instruction
that can accept the exception is decoded.
Table 5.11 Exception Source Generation Immediately after Delayed Branch Instruction
Exception Source
Point of Occurrence
FPU
Address Error exception
Register Bank
Error (Overflow) Interrupt
Immediately after a
Not accepted
delayed branch instruction^*
Not accepted Not accepted
Not accepted
Note: * Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF
Rev. 1.00 Nov. 14, 2007 Page 127 of 1262
REJ09B0437-0100