SH7670 Datasheet, PDF (666/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 17 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name
Value R/W Description
3 to 0 BWAIT[3:0] 1111
R/W CPU Bus Wait
On a Pφ basis, set the number of waits needed when
accessing registers of this module via the peripheral
bus.
0000: 0 wait (accessing two cycles on a Pφ basis)
0001: 1 wait (accessing three cycles on a Pφ basis)
0010: 2 waits (accessing four cycles on a Pφ basis)
:
1111: 15 waits (accessing 17 cycles on a Pφ basis)
Note: Be sure to set this bit in the initialization
routine of this module by taking into account
the Pφ and access size.
17.3.3 System Configuration Status Register (SYSSTS)
SYSSTS is a register that monitors the line status (D + and D − lines) of the USB data bus.
This register is initialized by a power-on reset or a USB bus reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LNST[1:0]
Initial value: 0
0
0
0
0
1
0
0
0
0
0
0
0
0
—
—
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit
Bit Name Initial Value R/W
15 to 11 
All 0
R
10

1
R
9 to 2 
All 0
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Reserved
This bit is always read as 1. The write value should
always be 1.
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.00 Nov. 14, 2007 Page 640 of 1262
REJ09B0437-0100