SH7670 Datasheet, PDF (815/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 17 USB 2.0 Host/Function Module (USB)
(5) Transaction Counter (For PIPE1 to PIPE5 in Reading Direction)
When the specified number of transactions have been completed in the data packet receiving
direction, this module recognizes that the transfer has ended. The transaction counter function is
available when the pipes assigned to the D0FIFO/D1FIFO port have been set in the direction of
reading data from the buffer memory. Two transaction counters are provided: one is the TRNCNT
register that specifies the number of transactions to be executed and the other is the current
counter that internally counts the number of executed transactions. When the current counter value
matches the number of the transactions specified in TRNCNT, reading the buffer memory is
enabled. The current counter of the transaction counter function is initialized by the TRCLR bit, so
that the transactions can be counted again starting from the beginning. The information read from
TRNCNT differs depending on the setting of the TRENB bit.
• TRENB = 0: The specified transaction counter value can be read.
• TRENB = 1: The current counter value indicating the internally counted number of executed
transactions can be read.
When operating the TRCLR bit, the following should be noted.
• If the transactions are being counted and PID = BUF, the current counter cannot be cleared.
• If there is any data left in the buffer, the current counter cannot be cleared.
(6) Response PID
The PID bits in DCPCTR and PIPEnCTR are used to set the response PID for each pipe.
The following shows this module operation with various response PID settings:
(a) Response PID settings when the host controller function is selected:
The response PID is used to specify the execution of transactions.
(i) NAK setting: Using pipes is disabled. No transaction is executed.
(ii) BUF setting: Transactions are executed based on the status of the buffer memory. For OUT
direction: If there are transmit data in the buffer memory, an OUT token is issued.
For IN direction: If there is an area to receive data in the buffer memory, an IN token is
issued.
(iii) STALL setting: Using pipes is disabled. No transaction is executed.
Setup transactions for the DCP are set with the SUREQ bit.
Rev. 1.00 Nov. 14, 2007 Page 789 of 1262
REJ09B0437-0100