SH7670 Datasheet, PDF (910/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 20 Host Interface (HIF)
Initial
Bit
Bit Name Value R/W Description
9
BMD
0
R/W HIFRAM Bank Mode
8
BSEL
0
R/W HIFRAM Bank Select
Controls the HIFRAM access mode.
00: Both an external device and the on-chip CPU can
access bank 0. When access by both of these
conflict, even though the access addresses differ,
access by the external device is processed before
access by the on-chip CPU. Bank 1 cannot be
accessed.
01: Both an external device and the on-chip CPU can
access bank 1. When access by both of these
conflict, even though the access addresses differ,
access by the external device is processed before
access by the on-chip CPU. Bank 0 cannot be
accessed.
10: An external device can access only bank 0 while
the on-chip CPU can access only bank 1.
11: An external device can access only bank 1 while
the on-chip CPU can access only bank 0.
7

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6

1
R
Reserved
This bit is always read as 1. The write value should
always be 1.
5
MD1
0/1
R
HIF Mode 1
Indicates whether this LSI was started up in HIF boot
mode or non-HIF boot mode. This bit stores the value
of the HIFMD pin sampled at a power-on reset
0: Started up in non-HIF boot mode (booted from the
memory connected to area 0)
1: Started up in HIF boot mode (booted from HIFRAM)
4, 3

All 0 R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.00 Nov. 14, 2007 Page 884 of 1262
REJ09B0437-0100