SH7670 Datasheet, PDF (916/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 20 Host Interface (HIF)
20.4.7 HIF Address Register (HIFADR)
HIFADR is a 32-bit register which indicates the address in HIFRAM to be accessed by an external
device. When using the LOCK bit setting in HIFMCR to specify consecutive access of HIFRAM,
auto-increment (+4) or auto-decrement (-4) of the address, according to the AI/AD bit setting in
HIFMCR, is performed automatically, and HIFADR is updated. HIFADR can be only read by the
on-chip CPU. Access to HIFADR by an external device should be performed with HIFADR
specified by bits REG5 to REG0 in HIFIDX and the HIFRS pin low.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
















Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0





A[10:2]


Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R
R
Initial
Bit
Bit Name Value R/W Description
31 to 11 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
10 to 2 A[10:2] All 0
R/W HIFRAM Address Specification
These bits specify the address of HIFRAM to be
accessed by an external device, with 32-bit boundary.
1, 0

All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Nov. 14, 2007 Page 890 of 1262
REJ09B0437-0100